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? semiconductor components industries, llc, 2016 october, 2017 ? rev. 5 1 publication order number: ar0238/d ar0238 ar0238: 1/2.7-inch 2.1 mp/full hd digital image sensor general description on semiconductor?s ar0238 is a 1/2.7 - inch cmos digital image sensor with an active ? pixel array of 1928hx1088v. it captures images in either linear or high dynamic range modes , with a rolling ? shutter readout. it includes sophisticated camera functions such as in ? pixel binning , windowing and both video and single frame modes. it is designed for both low light and high dynamic range scene performance . it is programmable through a simple two ? wire serial interface. the ar0238 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and hd video. features ? superior low ? light performance ? latest 3.0 m pixel with on semiconductor dr ? pix technology with dual conversion gain ? full hd support at up to 1080p 60 fps for superior video performance ? linear or high dynamic range capture ? supports line interleaved t1/t2 readout to enable hdr processing in isp chip ? support for external mechanical shutter ? on ? chip phase ? locked loop (pll) oscillator ? integrated position ? based color and lens shading correction ? slave mode for precise frame ? rate control ? stereo/3d camera support ? statistics engine ? data interfaces: four ? lane serial high ? speed pixel interface (hispi) differential signaling (slvs and hivcm), or parallel ? auto black level calibration ? high ? speed configurable context switching ? temperature sensor applications ? video recording and streaming ? 1080p60 (monitoring) video applications ? high dynamic range imaging table 1. key parameters parameter typical value optical format 1/2.7 ? inch (6.6 mm) active pixels 1928(h) x 1088(v) (16:9 mode) pixel size 3.0 m x 3.0 m color filter array rgb bayer, rgb ? ir shutter type electronic rolling shutter and grr input clock range 6 ? 48 mhz output clock maxi- mum 148.5 mp/s (4 ? lane hispi) 74.25 mp/s (parallel) output serial hispi 10 ? , 12 ? , 14 ? , 16 ? , or 20 ? bit parallel 10 ? , 12 ? bit frame rate 1080p 60 fps linear hispi 30 fps linear parallel 30 fps line interleaved hispi 15 fps line interleaved parallel responsivity 4.0 v/lux ? sec snr max 41 db max dynamic range up to 96 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.3 v ? 0.6 v (slvs), 1.7 v ? 1.9 v (hivcm) power consumption (typical) < 300mw line interleaved 1080p30 <190mw 1080p30 linear mode operating temperature ? 30 c to + 85 c junction package options 11.43x11.43 mm 48 ? pin mplcc recon die www. onsemi.com
ar0238 www. onsemi.com 2 plcc48 11.43x11.43 (hispi) case 776aq plcc48 11.43x11.43 (parallel) case 776as table 2. ordering information part number product description orderable product attribute description ar0238cssc12shra0 ? dr1 rgb color, 12 degree cra, mplcc, hispi dry pack, no protective film, low moq ar0238cssc12shra0 ? dp1 rgb color, 12 degree cra, mplcc, hispi dry pack, with protective film, low moq ar0238cssc12shra0 ? dr rgb color, 12 degree cra, mplcc, hispi without protective film ar0238cssc12shra0 ? dp rgb color, 12 degree cra, mplcc, hispi with protective film ar0238cssc12spra0 ? dr rgb color, 12 degree cra, mplcc, parallel without protective film ar0238cssc12spra0 ? dr1 rgb color, 12 degree cra, mplcc, parallel dry pack, no protective film, low moq AR0238CSSC12SUD20 rgb color, 12 degree cra, recon die rgb recon die ar0238irsh12sud20 rgb ? ir, 12 degree cra, recon die rgb ? ir recon die ar0238cssc12shrah3 ? gevb rgb color, 12 degree cra, hispi evaluation board note: see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. general description the on semiconductor ar0238 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a 1080p ? resolution image at 60 frames per second (fps) through the hispi port. in linear mode, it outputs 12 ? bit or 10 ? bit a ? law compressed raw data, using the parallel or serial (hispi) output port. in high dynamic range mode, it outputs two exposure values that the isp will combine into an hdr image. the device may be operated in video (master) mode or in single frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. the ar0238 includes additional features to allow application ? specific tuning: windowing and offset, auto black level correction, and on ? board temperature sensor. optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. the ar0238 is designed to operate over a wide temperature range of ? 30 c to +85 c junction. functional overview the ar0238 is a progressive ? scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on ? chip, phase ? locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 mhz. the maximum output pixel rate is 148.5 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor configured in linear mode, and in hdr mode.
ar0238 www. onsemi.com 3 row noise correction black level correction test pattern generator pixel defect correction digital gain and pedestal a ? law compression parallel hispi 12 bits 10 bits 12 12 adc data figure 1. block diagram of ar0238 user interaction with the sensor is through the two ? wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. the core of the sensor is a 2.1 mp active ? pixel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog ? to ? digital converter (adc). the output from the adc is a 12 ? bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the sensor also offers a high dynamic range mode of operation where two images and taken using different exposures. these images are output in from the sensor and the isp must combine them into one high dynamic range image.
ar0238 www. onsemi.com 4 1. all power supplies must be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two ? wire speed. 3. the parallel interface output pads can be left unconnected if the serial output interface is used. 4. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on the layout and design considerations. refer to the ar0237at demo headboard schematics for circuit recommendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. notes: flash slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n v dd _pll v dd _io v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd s data s clk extclk 1.5 k 2 1.5 k 2 trigger oe_bar reset_bar test to controller from controller master clock (6 ? 48 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground s addr v dd _slvs hispi power either 0.4 v (slvs) or 1.8 v (hiv cm ) 1 v dd _pll pll power 1 slvs3_p slvs3_n slvsc_p slvsc_n v dd v dd _slvs shutter figure 2. typical configuration: serial four ? lane hispi interface
ar0238 www. onsemi.com 5 1. all power supplies must be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two ? wire speed. 3. the serial interface output pads can be left unconnected if the parallel output interface is used. 4. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on the layout and design considerations. refer to the ar0237at demo headboard schematics for circuit recommendations. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. 6. i/o signals voltage must be configured to match v dd _io voltage to minimize any leakage currents. 7. the extclk input is limited to 6 ? 48 mhz. notes: frame_valid line_valid pixclk flash v dd _io v dd v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd extclk s data s clk 1.5 k 2 1.5 k 2 trigger oe_bar reset_bar test to controller from controller master clock (6 ? 48 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground d out [11:0] s addr pll power 1 v dd _pll v dd _pll shutter figure 3. typical configuration: parallel pixel data interface
ar0238 www. onsemi.com 6 6 7 8 9 10 11 12 13 14 15 16 17 18 44 45 46 47 48 1 2 3 4 5 42 41 40 39 38 37 36 35 34 33 32 31 19 30 29 28 27 26 25 24 23 22 21 20 slvsc_n slvs1_p slvs1_n slvs0_p slvs0_n vdd_slvs vdd slvs3_p slvs3_n slvs2_p slvs2_n slvsc_p dgnd vdd_pll extclk vaa agnd vdd_io vdd dgnd reserved vaa agnd dgnd saddr sdata test flash vdd_io vdd vdd_io shutter trigger oe_bar reset_bar sclk vdd_io vdd dgnd agnd vaa_pix vaa atest vaa vaa_pix agnd dgnd vdd (top view ? lead down) figure 4. hispi 48 ? lead mplcc package 43
ar0238 www. onsemi.com 7 table 3. pin descriptions, hispi 48 ? lead mplcc ds name mplcc pin type description slvsc_n 1 output hispi serial ddr clock differential n slvs1_p 2 output hispi serial data, lane 1, differential p slvs1_n 3 output hispi serial data, lane 1, differential n slvs0_p 4 output hispi serial data, lane 0, differential p slvs0_n 5 output hispi serial data, lane 0, differential n vdd_slvs 6 power 0.3 v ? 0.6 v or 1.7 v ? 1.9 v port to hispi output driver. set the high_vcm (r0x306e[9]) bit to 1 when configuring vdd_slvs to 1.7 v ? 1.9 v. dgnd 7, 14, 18, 32, 40 power digital ground vdd_pll 8 power pll power, 2.8 v nominal extclk 9 input external input clock vaa 10, 16, 35, 37 power analog power, 2.8 v nominal agnd 11, 17, 33, 39 power analog ground. vdd_io 12, 20, 30, 42 power i/o supply power, 1.8/2.8 v nominal vdd 13, 19, 31, 41, 43 power digital power, 1.8 v nominal reserved 15 ? reserved, nc flash 21 output flash control output test 22 input manufacturing test enable pin (connect to dgnd) sdata 23 i/o two ? wire serial data i/o saddr 24 input two ? wire serial address select. 0: 0x20. 1: 0x30 sclk 25 input two ? wire serial clock input reset_bar 26 input asynchronous reset (active low). all settings are restored to factory default. oe_bar 27 input output enable (active low) trigger 28 input exposure synchronization input shutter 29 output control for external mechanical shutter. can be left floating if not used. vaa_pix 34, 38 power pixel power, 2.8 v nominal atest 36 ? reserved, nc slvs3_p 44 output hispi serial data, lane 3, differential p slvs3_n 45 output hispi serial data, lane 3, differential n slvs2_p 46 output hispi serial data, lane 2, differential p slvs2_n 47 output hispi serial data, lane 2, differential n slvsc_p 48 output hispi serial ddr clock differential p note: the 36 thermal connection pads should be all soldered to dgnd plane for better thermal conductivity. refer to package dimensions for details..
ar0238 www. onsemi.com 8 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 44 45 46 47 48 1 2 3 4 5 42 41 40 39 38 37 36 35 34 33 32 31 0 3 19 28 27 26 25 24 23 22 21 20 dout6 dout7 dout8 dout9 dout10 dout11 dout0 dout1 dout2 dout3 dout4 dout5 dgnd vdd_pll extclk vaa agnd vdd_io vdd dgnd reserved vaa agnd vdd dgnd test frame_valid pixclk flash vdd_io vdd vdd_io sclk saddr line_valid sdata vdd_io (top view ? lead down) vdd dgnd agnd vaa_pix vaa agnd atest shutter trigger oe_bar rest_bar figure 5. 48 ? lead parallel mplcc 29
ar0238 www. onsemi.com 9 table 4. 48 ? lead parallel mplcc name mplcc pin type description dout6 1 output data output 6 dout7 2 output data output 7 dout8 3 output data output 8 dout9 4 output data output 9 dout10 5 output data output 10 dout11 6 power data output 11 dgnd 7, 14, 24, 40 power digital ground vdd_pll 8 power pll power, 2.8 v nominal extclk 9 input external input clock vaa 10, 16, 37 power analog power, 2.8 v nominal agnd 11, 17, 36, 39 power analog ground vdd_io 12, 19, 29, 42 power i/o supply power, 1.8/2.8 v nominal vdd 13, 18, 30, 41 power digital power, 1.8 v nominal reserved 15 ? reserved, nc flash 20 power flash control output pixclk 21 output pixel clock frame_valid 22 output frame valid test 23 input manufacturing test enable pin (connect to dgng) sdata 25 i/o two ? wire serial data i/o line_valid 26 output line valid saddr 27 input two ? wire serial address select. 0: 0x20, 1: 0x30 sclk 28 input two ? wire serial clock input reset_bar 31 input asynchronous reset (active low). all settings are restored to factory default oe_bar 32 input output enable (active low) trigger 33 input exposure synchronization input shutter 34 output control for external mechanical shutter. can be left floating if not used. atest 35 ? reserved, nc vaa_pix 38 power pixel power, 2.8 v nominal dout0 43 output data output 0 dout1 44 output data output 1 dout2 45 output data output 2 dout3 46 output data output 3 dout4 47 output data output 4 dout5 48 output data output 5 note: the 29 thermal connection pads should be all soldered to dgnd plane for better thermal conductivity. refer to package dimensions for details.
ar0238 www. onsemi.com 10 pixel data format pixel array structure while the sensor?s format is 1928 x1088, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the pixel adjustment is always performed for mono ? chrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. 1944 1116 light dummy pixel active pixel 10 barrier + 4 border pixels 1928 1088 5.78 3.26 mm 2 barrier + 6 border pixels 10 barrier + 4 border pixels 2 barrier + 6 border pixels figure 6. pixel array description
ar0238 www. onsemi.com 11 active pixel (0,0) array pixel (0, 0) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction figure 7. pixel color pattern detail (rgb) (top right corner) figure 8. pixel color pattern detail (rgb ? ir) (top right corner) g b g r column readout direction row readout direction active pixel (0, 0) array pixel (0, 0) g b r g g ir g ir g ir g ir g r g b r g g ir g ir g ir g ir g b default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 7). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in default condition is that of pixel (10, 14). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 9. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in figure 9.
ar0238 www. onsemi.com 12 lens pixel (0,0) row readout order column readout order scene sensor (rear view) figure 9. imaging a scene features overview for a complete description , recommendations, and usage guidelines for product features, refer to the ar0238 developer guide. 3.0 m dual conversion gain pixel to improve the low light performance and keep the high dynamic range, a large (3.0 um) dual conversion gain pixel is implemented for better image optimization. with a dual conversion gain pixel , the conversion gain of the pixel may be dynamically changed to better adapt the pixel response based on dynamic range of the scene . this gain can be switched manually or automatically by an auto exposure control module. hdr by default, the sensor powers up in linear mode. one can change to hdr mode. the hdr scheme used is multi ? exposure hdr. this allows the sensor to handle up to 96 db of dynamic range. in hdr mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. the exposure ratio may be set to 4x, 8x, 16x, or 32x. sensor also provides flexibility to choose any exposure ratio by setting number of t2 exposure rows indepen ? dent of the t1 exposure. the data will be output as line interleaved data as described in the t1/t2 line interleaved mode section. there is also an option to output either t1 only or t2 only. resolution the active array supports a maximum of 1928x1088 pixels to support 1080p resolution. utilizing a 3.0 um pixel will result in an optical format of 1/2.7 ? inch (approximately 6.6 mm diagonal). frame rate at full (1080p) resolution, the ar0238 is capable of running up to 60 fps in linear mode and 30 fps in line interleaved mode. image acquisition mode the ar0238 supports two image acquisition modes: ? electronic rolling shutter (ers) mode this is the normal mode of operation. when the ar0238 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when ers mode is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between reset ? ting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. when the integration time is changed (by using the two ? wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the ar0238 switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? in the ar0238 register reference. ? global reset mode. this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the ar0238 provides control signals to interface to that shutter. the benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ers operation. visual artifacts arise in ers operation, particularly at low frame rates, because an ers image ef fectively integrates each row of the pixel array at a different point in time. embedded data and statistics the ar0238 has the capability to output image data and statistics embedded within the frame timing . there are two types of information embedded within the frame readout.
ar0238 www. onsemi.com 13 ? embedded data: if enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. ? embedded statistics: if enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. multi ? camera synchronization slave mode the slave mode feature of the ar0238 supports triggering the start of a frame readout from an input signal that is supplied from an external asic. the slave mode signal allows for precise control of frame rate and register change updates . context switching and register updates the user has the option of using the highly configurable context memory , or a simplified implementation in which only a subset of registers is available for switching . the ar0238 supports a highly configurable context switching ram of size 256 x 16 . within this context memory , changes to any register may be stored. the register set for each context must be the same , but the number of contexts and registers per context are limited only by the size of the context memory . alternatively, the user may switch between two predefined register sets a and b by writing to a context switch change bit . when the context switch is configured to context a the sensor will reference the context a registers . if the context switch is changed from a to b during the readout of frame n, the sensor will then reference the context b coarse_integration_time registers in frame n+1 and all other context b registers at the beginning of reading frame n+2 . the sensor will show the same behavior when changing from context b to context a . the registers listed in table 5 are context ? switchable: table 5. list of configurable registers for context a and context b context a context b register description register description coarse_integration_time coarse_integration_time_cb line_length_pck line_length_pck_cb frame_length_lines frame_length_lines_cb row_bin row_bin_cb col_bin col_bin_cb fine_gain fine_gain_cb coarse_gain coarse_gain_cb coarse_integration_time2 coarse_integration_time2_cb dcg_manual_set dcg_manual_set_cb dcg_manual_set_t1 dcg_manual_set_t1_cb bypass_pix_comb bypass_pix_cb coarse_gain_t1 coarse_gain_t1_cb fine_gain_t1 fine_gain_t1_cb x_addr_start x_addr_start_cb y_addr_start y_addr_start_cb x_addr_end x_addr_end_cb y_addr_end y_addr_end_cb y_odd_inc y_odd_inc_cb x_odd_inc x_odd_inc_cb green1_gain green1_gain_cb blue_gain blue_gain_cb red_gain red_gain_cb green2_gain green2_gain_cb global_gain global_gain_cb operation_mode_ctrl operation_mode_ctrl_cb bypass_pix_comb bypass_pix_comb_cb
ar0238 www. onsemi.com 14 analog/digital gains a programmable analog gain of 1.0x to 16x (linear and hdr) applied simultaneously to all color channels will be featured along with a digital gain of 1x to 16x that may be configured on a per color channel basis . analog gain can be applied per exposure in line interleaved mode. skipping/binning modes the ar0238 supports subsampling. subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. horizontal binning is achieved in the digital readout. the sensor will sample the combined 2x adjacent pixels within the same color plane. vertical row binning is applied in the pixel readout. row binning can be configured as 2x rows within the same color plane. pixel skipping can be configured up to 2x in both the x ? direction and y ? direction. skipping pixels in the x ? direction will not reduce the row time. skipping pixels in the y direction will reduce the number of rows from the sensor effectively reducing the frame time. skipping will introduce image artifacts from aliasing . the ar0238 supports row wise vertical binning. row wise vertical summing is only supported in monochrome sensors. clocking options the sensor contains a phase ? locked loop (pll) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre ? pll clock divider followed by a multiplier . the pll multiplier should be an even integer. if an odd integer (m) is programmed, the pll will default to the lower (m ? 1) value to maintain an even multiplier value. the multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces . use of the pll is required when using the hispi interface. temperature sensor the ar0238 sensor has a built - in ptat - based temperature sensor , accessible through registers, that is capable of measuring die junction temperature . the value read out from the temperature sensor register is an adc output value that needs to be converted downstream to a final temperature value in degrees celsius . since the ptat device characteristic response is quite linear in the temperature range of operation required, a simple linear function can be used to convert the adc output value to the final temperature in degrees celsius . a single reference point will be made available via register read as well as a slope for back ? calculating the junction temperature value . an error of +/ - 5% or better over the full specified operating range of the sensor is to be expected . silicon / firmware / sequencer revision information a revision register will be provided to read out (via i 2 c) silicon and sequencer/otpm revision information. this will be helpful to distinguish among dif ferent lots of material if there are future otpm or sequencer revisions. lens shading correction the latest lens shading correction algorithm will be included for potential low z height applications. compression when the ar0238 is configured for linear mode operation, the sensor can optionally compress 12 ? bit data to 10 ? bit using a ? law compression. the a ? law compression is disabled by default. packaging the ar0238 will be offered in a 11.43 x 11.43 48 ? lead mplcc package. parallel interface the parallel pixel data interface uses these output ? only signals: ? frame_valid ? line_valid ? pixclk ? dout[11:0] high speed serial pixel (hispi) interface the hispi interface supports three protocols, streaming ? s, streaming ? sp , and packetized sp. the streaming protocols conform to a standard video application where each line of active or intra ? frame blanking provided by the sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line ? to ? line and frame ? to ? frame blanking data. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes . the ar0238 supports serial data widths of 10 or 12 bits on one, two, or four lanes . the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers . once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in pcb design. delay compensation may be set for clock and/or data lines in the hispi_timing register r0x31c0. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x 0000 to reduce jitter, skew , and power dissipation.
ar0238 www. onsemi.com 15 sensor control interface the two ? wire serial interface bus enables read/write access to control and status registers within the ar0238. the interface protocol uses a master/slave model in which a master controls one or more slave devices . the sensor acts as a slave device . the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off ? chip by a 1 . 5 k resistor. either the slave or master device can drive s data low ? the interface protocol determines which device is allowed to drive s data at any given time. the two ? wire serial interface can run at 1 00 khz or 400 khz. t1/t2 line interleaved mode the ar0238 outputs the t1 and t2 exposures separately, in a line interleaved format. the purpose of this is to enable off chip hdr linear combination and processing . see the ar0238 developer guide for more information. wavelength (nm) 350 quantum efficiency (%) 450 550 650 750 850 950 1050 1150 0 10 20 30 40 50 60 70 red green (r) green (b) blue figure 10. quantum efficiency ? rgb
ar0238 www. onsemi.com 16 wavelength (nm) 350 quantum efficiency (%) 450 550 650 750 850 950 1050 1150 0 10 20 30 40 50 60 70 red green (r) green (b) blue ir figure 11. quantum efficiency ? rgb ? ir electrical specifications unless otherwise stated, the following specifications apply under the following conditions: vdd = 1.8 v ? 0. 10/+ 0 .15; vdd_io = vdd_pll = vaa = vaa_pix = 2 . 8 v 0.3 v; vdd_slvs = 0.4 v ? 0.1/+0.2; t a = ? 40 c to +85 c ? ; output load = 10 pf; frequency = 74.25 mhz; hispi off. two ? wire serial register interface the electrical characteristics of the two ? wire serial register interface (s clk , s data ) are shown in figure 12 and table 6. s data s clk s sr p s t f t r t f t r t su;dat t hd;sta t su;sto t su;sta t buf t hd;dat t high t low t hd;sta note: read sequence: for an 8 ? bit read, read waveforms start after write command and register address are issued. figure 12. two ? wire serial bus timing parameters
ar0238 www. onsemi.com 17 table 6. two ? wire serial bus characteristics fextclk = 27 mhz; vdd = 1.8 v; vdd_io = 2.8 v; vaa = 2.8 v; vaa_pix = 2.8 v; vdd_pll = 2 . 8 v; t a = 25 c parameter symbol standard mode fast mode unit min max min max sclk clock frequency fscl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated thd;sta 4.0 ? 0.6 ? s low period of the sclk clock tlow 4.7 ? 1.3 ? s high period of the sclk clock thigh 4.0 ? 0.6 ? s set ? up time for a repeated start condition tsu;sta 4.7 ? 0.6 ? s data hold time thd;dat 0 (note 11) 3.45 (note 12) 0 (note 13) 0.9 (note 12) s data set ? up time tsu;dat 250 ? 100 (note 13) ? ns rise time of both sdata and sclk signals tr ? 1000 20 + 0.1cb (note 14) 300 ns fall time of both sdata and sclk signals tf ? 300 20 + 0.1cb (note 14) 300 ns set ? up time for stop condition tsu;sto 4.0 ? 0.6 ? s bus free time between a stop and start condition tbuf 4.7 ? 1.3 ? s capacitive load for each bus line cb ? 400 ? 400 pf serial interface input pin capacitance cin_si ? 3.3 ? 3.3 pf s data max load capacitance cload_sd ? 3 0 ? 3 0 pf s data pull ? up resistor rsd 1.5 4.7 1.5 4.7 k 8. this table is based on i2c standard (v2.1 january 2000). philips semiconductor. 9. two ? wire control is i2c ? compatible. 10. all values referred to vihmin = 0.9 vdd and vilmax = 0.1 vdd levels. sensor exclk = 27 mhz. 11. a device must internally provide a hold time of at least 300 ns for the sdata signal to bridge the undefined region of the f alling edge of sclk. 12. the maximum thd;dat has only to be met if the device does not stretch the low period (tlow) of the sclk signal. 13. a fast ? mode i2c ? bus device can be used in a standard ? mode i2c ? bus system, but the requirement tsu;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the sclk signal. if such a device does stretch the low period of the sclk signal, it must output the next data bit to the sdata line tr max + tsu;dat = 1000 + 250 = 1250 ns (accordin g to the standard ? mode i2c ? bus specification) before the sclk line is released. 14. cb = total capacitance of one bus line in pf.
ar0238 www. onsemi.com 18 i/o timing by default, the ar0238 launches pixel data, fv, and lv with the falling edge of pixc lk. the expectation is that the user captures dout[1 1:0], fv, and lv using the rising edge of pixclk. see figure 13 below and table 7 on page 18 for i/o timing (ac) characteristics. extclk pixclk data[11:0] line_valid/ frame_valid pxl_0 pxl_1 pxl_2 pxl_n t pfl t pll t fp t rp t f t r 90% 90% 90% 90% 10% 10% 10% 10% t extclk t pd t plh t pfh frame_valid leads line_valid by 6 pixclks frame_valid trails line_valid by 6 pixclks figure 13. i/o timing diagram table 7. i/o timing characteristics symbol definition condition min typ max unit f extclk1s input clock frequency 6 ? 48 mhz t extclk1 input clock period 20.8 ? 166 ns t r input clock rise time ? 3 ? ns t f input clock fall time ? 3 ? ns t rp pixclk rise time 2 3.5 5 ns t fp pixclk fall time 2 3.5 5 ns clock duty cycle 45 50 55 % t cp extclk to pixclk propagation delay nominal voltages, pll disabled 10 14 18 ns f pixclk pixclk frequency default, nominal voltages 6 ? 74.25 mhz t pd pixclk to data valid default, nominal voltages 0 2.5 5 ns t pfh pixclk to fv high default, nominal voltages ? 2 3 6 ns t plh pixclk to lv high default, nominal voltages ? 2 3 6 ns t pfl pixclk to fv low default, nominal voltages ? 2 2.5 6 ns t pll pixclk to lv low default, nominal voltages ? 2 2.5 6 ns c load output load capacitance ? <10 ? pf c in input pin capacitance ? 2.5 ? pf note: i/o timing characteristics are measured under the following conditions: ? temperature is 25 c ambient ? 10 pf load ? 1 . 8 v i/o supply voltage
ar0238 www. onsemi.com 19 dc electrical characteristics the dc electrical characteristics are shown in the tables below. table 8. dc electrical characteristics symbol definition condition min typ max unit vdd core digital voltage 1.7 1.8 1.95 v vdd_io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v vaa analog voltage 2.5 2.8 3.1 v vaa_pix pixel supply voltage 2.5 2.8 3.1 v vdd_pll pll supply voltage 2.5 2.8 3.1 v vdd_slvs hispi supply voltage 0.3 0.4 0.6 v vih input high voltage vdd_io*0.7 ? ? v vil input low voltage ? ? vdd_io*0.3 v iin input leakage current no pull ? up resistor; vin = vdd_io or dgnd 20 ? ? a voh output high voltage vdd_io ? 0.3 ? ? v vol output low voltage ? ? 0.4 v ioh output high current at specified voh ? 22 ? ? ma iol output low current at specified vol ? ? 22 ma table 9. absolute maximum ratings symbol definition condition min max unit vdd_max core digital voltage ?0.3 2.4 v vdd_io_max i/o digital voltage ?0.3 4 v vaa_max analog voltage ?0.3 4 v vaa_pix pixel supply voltage ?0.3 4 v vdd_pll pll supply voltage ?0.3 4 v vdd_slvs_max hispi i/o digital voltage ?0.3 2.4 v tst storage temperature ?40 85 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
ar0238 www. onsemi.com 20 table 10. 1080p30 linear 74 mhz parallel 2.8 v (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = v dd _io = 2.8 v; v dd = 1.8 v; pll enabled and pixclk = 74.25 mhz; low power mode enabled; t a = 25 c) definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 i dd 1.8 20 34 50 ma i/o digital operating current streaming 1080p30 i dd _io 2.8 15 28 50 ma analog operating current streaming 1080p30 i aa 2.8 15 26 50 ma pixel supply current streaming 1080p30 i aa _pix 2.8 1 3 7 ma pll supply current streaming 1080p30 i dd _pll 2.8 5.5 6.4 7 ma power 138.2 238.72 409.2 mw table 11. 1080p30 linear 74 mhz parallel 1.8 v (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = 1.8 v; pll enabled and pixclk = 74.25 mhz; low power mode enabled; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 i dd 1.8 20 34 50 ma i/o digital operating current streaming 1080p30 i dd _io 1.8 10 14 30 ma analog operating current streaming 1080p30 i aa 2.8 15 26 50 ma pixel supply current streaming 1080p30 i aa _pix 2.8 1 3 7 ma pll supply current streaming 1080p30 i dd _pll 2.8 5.5 6.4 7 ma power 114.2 185.52 323.2 mw table 12. 1080p30 linear 74 mhz hispi slvs (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = 1.8 v; v dd _slvs = 0.4 v; pll enabled and pixclk = 74.25 mhz; 4 ? lane hispi mode; low power mode enabled; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 i dd 1.8 25 44 65 ma analog operating current streaming 1080p30 i aa 2.8 15 26 50 ma pixel supply current streaming 1080p30 i aa _pix 2.8 1 3 7 ma pll supply current streaming 1080p30 i dd _pll 2.8 6 7.5 8.5 ma slvs supply current streaming 1080p30 i dd _slvs 0.4 6 9.5 14 ma power 109 185.2 306 mw table 13. 1080p30 linear 74 mhz hispi hiv cm (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = v dd _slvs = 1.8 v; pll enabled and pixclk = 74.25 mhz; 4 ? lane hispi mode; low power mode enabled; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 i dd 1.8 25 44 65 ma analog operating current streaming 1080p30 i aa 2.8 15 26 50 ma pixel supply current streaming 1080p30 i aa _pix 2.8 1 3 7 ma pll supply current streaming 1080p30 i dd _pll 2.8 6 7.5 8.5 ma slvs supply current streaming 1080p30 i dd _slvs 1.8 12 20 35 ma power 128.2 217.4 363.4 mw
ar0238 www. onsemi.com 21 table 14. 1080p60 linear 74 mhz hispi slvs (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = 1.8 v; v dd _slvs = 0.4 v; pll enabled and pixclk = 74.25 mhz; 4 ? lane hispi mode; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p60 i dd 1.8 50 88 130 ma analog operating current streaming 1080p60 i aa 2.8 20 36 60 ma pixel supply current streaming 1080p60 i aa _pix 2.8 1 4 8 ma pll supply current streaming 1080p60 i dd _pll 2.8 7 8.5 9.5 ma slvs supply current streaming 1080p60 i dd _slvs 0.4 6 9.5 14 ma power 170.8 298 442.6 mw table 15. 1080p60 linear 74 mhz hispi hiv cm (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = 1.8 v; v dd _slvs = 1.8 v; pll enabled and pixclk = 74.25 mhz; 4 ? lane hispi mode; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p60 i dd 1.8 50 88 130 ma analog operating current streaming 1080p60 i aa 2.8 20 36 60 ma pixel supply current streaming 1080p60 i aa _pix 2.8 1 4 8 ma pll supply current streaming 1080p60 i dd _pll 2.8 7 8.5 9.5 ma slvs supply current streaming 1080p60 i dd _slvs 1.8 12 20 35 ma power 190 330.2 500 mw table 16. 1080p30 line ? inleaved 74mhz hispi slvs (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = 1.8 v; v dd _slvs = 0.4 v; pll enabled and pixclk = 74.25 mhz; 4 ? lane hispi mode; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 i dd 1.8 50 88 130 ma analog operating current streaming 1080p30 i aa 2.8 20 36 60 ma pixel supply current streaming 1080p30 i aa _pix 2.8 1 4 8 ma pll supply current streaming 1080p30 i dd _pll 2.8 7 8.5 9.5 ma slvs supply current streaming 1080p30 i dd _slvs 0.4 6 9.5 14 ma power 170.8 298 442.6 mw table 17. 1080p30 line ? inleaved 74mhz hispi hiv cm (operating currents are measured in ma at the following conditions: v aa = v aa _pix = v dd _pll = 2.8 v; v dd = v dd _io = 1.8 v; v dd _slvs = 1.8 v; pll enabled and pixclk = 74.25 mhz; 4 ? lane hispi mode; t a = 25 c dark image, 8 analog gain, hcg, 20 ms integration time) definition condition symbol voltage min typ max unit digital operating current streaming 1080p30 i dd 1.8 50 88 130 ma analog operating current streaming 1080p30 i aa 2.8 20 36 60 ma pixel supply current streaming 1080p30 i aa _pix 2.8 1 4 8 ma pll supply current streaming 1080p30 i dd _pll 2.8 7 8.5 9.5 ma slvs supply current streaming 1080p30 i dd _slvs 1.8 12 20 35 ma power 190 330.2 500 mw
ar0238 www. onsemi.com 22 hispi electrical specifications the on semiconductor ar0238 sensor supports both slvs and hivcm hispi modes. refer to the high - speed serial pixel (hispi) interface physical layer specification v2. 00.00 for electrical definitions, specifications, and timing information . the v dd _slvs supply in this datasheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the dll as implemented on ar0238 is limited in the number of available delay steps and differs from the hispi specification as described in this section. table 18. channel skew measurement conditions: vdd_hispi = 1.8 v; vdd_hispi_tx = 0.4v; data rate = 480 mbps; dll set to 0 data lane skew in reference to clock tchskew1phy ? 150 ps
ar0238 www. onsemi.com 23 power ? on reset and standby timing power ? up sequence the recommended power ? up sequence for the ar0238 is shown in figure 14. the available power supplies (vdd_io, vdd, vdd_slvs, vdd_pll, vaa, vaa_pix) must have the separation specified below. 1. turn on vdd_pll power supply. 2. after 100 s, turn on vaa and vaa_pix power supply. 3. 3. after 100 s, turn on vdd_io power supply. 4. after 100 s, turn on vdd power supply. 5. after 100 s, turn on vdd_slvs power supply. 6. after the last power supply is stable, enable extclk. 7. assert reset_bar for at least 1 ms. the parallel interface will be tri ? stated during this time. 8. wait 150000 extclks (for internal initialization into software standby. 9. configure pll, output, and image settings to desired values. 10. wait 1ms for the pll to lock. 11. set streaming mode (r0x301a[2] = 1). extclk v dd _slvs (0.4) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _pll (2.8) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t x hard reset internal initialization software standby pll lock streaming reset_bar figure 14. power up table 19. power ? up sequence definition symbol min typ max unit vdd_pll to vaa/vaa_pix (note 17) t0 0 100 ? s vaa/vaa_pix to vdd_io t1 0 100 ? s vdd_io to vdd t2 0 100 ? s vdd to vdd_slvs t3 0 100 ? s xtal settle time tx ? 30 (note 15) ? ms hard reset t4 1 (note 16) ? ? ms internal initialization t5 150000 ? ? extclk s pll lock time t6 1 ? ? ms 15. xtal settling time is component ? dependent, usually taking about 10 ? 100 ms. 16. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc time must include the all power rail settle time and xtal settle time. 17. it is critical that vdd_pll is not powered up after the other power supplies. it must be powered before or at least at the s ame time as the others. if the case happens that vdd_pll is powered after other supplies then sensor may have functionality issues and will exp erience high current draw on this supply.
ar0238 www. onsemi.com 24 power ? down sequence the recommended power ? down sequence for the ar0238 is shown in figure 15 . the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. turn off vdd_slvs. 4. turn off vdd. 5. turn off vdd_io. 6. turn off vaa/vaa_pix. 7. turn off vdd_pll. extclk v dd _pll (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) t 0 power down until next power up cycle t 1 t 2 t 3 t 4 v aa _pix v aa (2.8) figure 15. power down table 20. power ? down sequence definition symbol min typ max unit vdd_slvs to vdd t0 0 ? ? s vdd to vdd_io t1 0 ? ? s vdd_io to vaa/vaa_pix t2 0 ? ? s vaa/vaa_pix to vdd_pll t3 0 ? ? s power down until next power up time t4 100 ? ? ms note: t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharge d .
ar0238 www. onsemi.com 25 package dimensions plcc48 11.43x11.43 (hispi) case 776aq issue d
ar0238 www. onsemi.com 26 package dimensions plcc48 11.43x11.43 (parallel) case 776as issue a on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ar0238/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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